I am part of the Robust Low Power VLSI (RLPVLSI) group headed by Dr. Ben Calhoun. My current research interests are SRAM design in general and 5-transistor bitcells in particular. I am also involved in the design of a novel SRAM tool.
I taped out a chip in 90nm in April 2007 and am busy testing it. Another chip taped out in 45nm in August 2007 is expected back early 2008.
Publications:
1. J.Wang, S.Nalam, B.H. Calhoun, "Analyzing Static and Dynamic Write Margin for Nanometer SRAMs", ISLPED, August 2008
